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GPU:(PS3 vs X-BOX360 vs NRev) +Wird NRev stärkste Konsole?
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nighty
L19: Master
Weil es nachgebessert wurde? 
Mit Photoshop lässt sich viel machen...
Mit Photoshop lässt sich viel machen...
nighty
L19: Master
klar und dem glaubst du?
Sony sagt auch Killzone und Motorstorm sind Echtzeit... ob man dies glauben kann?
Doppelmoral mancher MS Fanboys...
Sony sagt auch Killzone und Motorstorm sind Echtzeit... ob man dies glauben kann?
Doppelmoral mancher MS Fanboys...
DotProduct
L05: Lazy
- Seit
- 24 Mai 2005
- Beiträge
- 286
Instruction set
Programs running inside the SPU need to be rather simplistic and self-contained, so you don't need complicated access protection or different privilege modes in the SPU itself. As a consequence, the instruction set contains mostly arithmetic and branch operations but none that resemble kernel mode instructions of the PPE.
Also, exceptions resulting from executed code aren't reported to the SPU itself. If a serious error occurs, for example, an invalid opcode, the SPU is stopped and an interrupt is delivered to the PPE. Some of the common sources of exceptions are not even possible on the SPU. For example, there are no addressing exceptions since all pointers get aligned and truncated to the local store size when attempting a memory access.
The arithmetic vector operations are similar to the VMX operations of the PPE, and you can use them for highly optimized video, image processing, or scientific applications, among others.
The main communication method of the SPU with other parts of the Cell processor is defined by a number of "channels." Each channel has a predefined function and is either a read channel or a write channel.
For example, a mailbox mechanism is a basic communication method between the SPE and the PPE. The SPU has a read channel for receiving a single data word from the mailbox and two write channels for sending data words (more on this below). One of those write channels is defined to generate external interrupts on the CPU when data is available, and the other does not have a notification mechanism.
When an SPU tries to read from an empty mailbox, it will stop execution until some value is written to its memory-mapped register.
When the PPE wants to access the mailbox, it needs to have access to the memory-mapped register space, which is normally only available to kernel space. It has three mailbox registers for each SPU, and each of those accesses one of the three SPU mailbox channels.
The memory-mapped registers are used by the PPE to control certain aspects of an SPE, but are not accessible by the SPU code itself. For example, one PPE-side mailbox register appears as a write-only physical memory location. When the PPE writes a data word to that address, the SPU can read from its corresponding mailbox read channels.
Other channels are used to access virtual memory associated with a user context on the PPE. By writing to DMA channels, the SPE can initiate a memory transfer, which is executed in parallel to both the SPU code execution and the PPE control flow. Only when a page fault is hit, for example, because the accessed page has been swapped out to disk, does the PPE receive an interrupt.
--------------------
http://www-128.ibm.com/developerworks/linux/library/pa-cell/index.html?
--------------------
Soviel zu: Auf einer SPU kann ein vollwertiges Multitasking OS laufen.
##
Since the SPU instruction set is not directly related to an existing CPU architecture, a new back end was written for both GCC and binutils. SPU code is compiled separately from the PPC code and gets loaded at run time.
##
Debugger
Debugging SPU programs creates a new set of problems. While it would be relatively easy to create a new GDB target for the SPU itself, most users need to debug interaction between PPE and SPE. The approach we are taking here is to enable GDB to support multiple targets in one binary, and change the PowerPC target to know about spufs. When the PowerPC debugger finds a program running SPU_RUN ioctl call, it switches to the SPU back-end code and works on the SPU context instead of the main program context.
Profiler
While there currently is no working profiler for spufs programs, we have plans to extend OProfile to cover mixed PPE/SPE programs. This requires changes to the OProfile kernel code to sample the SPU instruction pointers regularly.
On the userspace side of OProfile, it needs an extra indirection level to come from the spufs file to the actual ELF file that was loaded into that.
####
Das ist von Linux Cell Entwicklern und zeichnet ein relativ genaues Bild über die Realität des Cell Prozessors.
Programs running inside the SPU need to be rather simplistic and self-contained, so you don't need complicated access protection or different privilege modes in the SPU itself. As a consequence, the instruction set contains mostly arithmetic and branch operations but none that resemble kernel mode instructions of the PPE.
Also, exceptions resulting from executed code aren't reported to the SPU itself. If a serious error occurs, for example, an invalid opcode, the SPU is stopped and an interrupt is delivered to the PPE. Some of the common sources of exceptions are not even possible on the SPU. For example, there are no addressing exceptions since all pointers get aligned and truncated to the local store size when attempting a memory access.
The arithmetic vector operations are similar to the VMX operations of the PPE, and you can use them for highly optimized video, image processing, or scientific applications, among others.
The main communication method of the SPU with other parts of the Cell processor is defined by a number of "channels." Each channel has a predefined function and is either a read channel or a write channel.
For example, a mailbox mechanism is a basic communication method between the SPE and the PPE. The SPU has a read channel for receiving a single data word from the mailbox and two write channels for sending data words (more on this below). One of those write channels is defined to generate external interrupts on the CPU when data is available, and the other does not have a notification mechanism.
When an SPU tries to read from an empty mailbox, it will stop execution until some value is written to its memory-mapped register.
When the PPE wants to access the mailbox, it needs to have access to the memory-mapped register space, which is normally only available to kernel space. It has three mailbox registers for each SPU, and each of those accesses one of the three SPU mailbox channels.
The memory-mapped registers are used by the PPE to control certain aspects of an SPE, but are not accessible by the SPU code itself. For example, one PPE-side mailbox register appears as a write-only physical memory location. When the PPE writes a data word to that address, the SPU can read from its corresponding mailbox read channels.
Other channels are used to access virtual memory associated with a user context on the PPE. By writing to DMA channels, the SPE can initiate a memory transfer, which is executed in parallel to both the SPU code execution and the PPE control flow. Only when a page fault is hit, for example, because the accessed page has been swapped out to disk, does the PPE receive an interrupt.
--------------------
http://www-128.ibm.com/developerworks/linux/library/pa-cell/index.html?
--------------------
Soviel zu: Auf einer SPU kann ein vollwertiges Multitasking OS laufen.
##
Since the SPU instruction set is not directly related to an existing CPU architecture, a new back end was written for both GCC and binutils. SPU code is compiled separately from the PPC code and gets loaded at run time.
##
Debugger
Debugging SPU programs creates a new set of problems. While it would be relatively easy to create a new GDB target for the SPU itself, most users need to debug interaction between PPE and SPE. The approach we are taking here is to enable GDB to support multiple targets in one binary, and change the PowerPC target to know about spufs. When the PowerPC debugger finds a program running SPU_RUN ioctl call, it switches to the SPU back-end code and works on the SPU context instead of the main program context.
Profiler
While there currently is no working profiler for spufs programs, we have plans to extend OProfile to cover mixed PPE/SPE programs. This requires changes to the OProfile kernel code to sample the SPU instruction pointers regularly.
On the userspace side of OProfile, it needs an extra indirection level to come from the spufs file to the actual ELF file that was loaded into that.
####
Das ist von Linux Cell Entwicklern und zeichnet ein relativ genaues Bild über die Realität des Cell Prozessors.
nighty
L19: Master
tja... IBM sagt nunmal was anderes
PacoLucia
L15: Wise
- Seit
- 14 Apr 2004
- Beiträge
- 9.428
Also Justy ist 100%ig ein alter Bekannter.
Normalerweise würde ich auch zocker tippen, da er zu 100% den identischen schwachsinnigen Diskussionstiel hat.
Dieses Aussage hat ihn entlarvt:
Und wenn es nicht Zocker ist, ist er genausoschlimm oder sogar nochschlimmer.
Normalerweise würde ich auch zocker tippen, da er zu 100% den identischen schwachsinnigen Diskussionstiel hat.
Dieses Aussage hat ihn entlarvt:
Exakt den selben absoluten Schwachsinn hat Zocker 2 (^^) nach der E3 geschrieben.
Und wenn es nicht Zocker ist, ist er genausoschlimm oder sogar nochschlimmer.
nightelve schrieb:
Sie sagen mit 5 FPS auf dem DevKit gelaufen. JA das glaube ich.
Ben sagt (der noch nie in der beziehung gelogen hat) das dies SO im Spiel aussehen wird. Und jetzt lieber Nightelve will ich mal fakten sehen. Entweder ich bekomme einen Link in dem steh das hier nachgebessert worden ist und das von einer guten Quelle oder Du lässt die Kommentare. Denn ich bin gerade überrascht wegen Dir.
Wo ist die glaubwürdige quelle?
Justy schrieb:nightelve schrieb:Weil es nachgebessert wurde?
Sagt wer? Laut Ben sieht es so im Spiel aus.
Wenn es wirklich so im fertigen Spiel aussieht, dann Hut ab.
Aber an Motorstorm kommts es imo nicht ran
Cell schrieb:Justy schrieb:nightelve schrieb:Weil es nachgebessert wurde?
Sagt wer? Laut Ben sieht es so im Spiel aus.
Wenn es wirklich so im fertigen Spiel aussieht, dann Hut ab.
Aber an Motorstorm kommts es imo nicht ran
Tja, nur hat noch keiner gesagt das Motorstorm so im Spiel aussehen wird, geht auch nicht. Das war ein Script, ein Intro oder sonst was. Nicht falsch verstehen, ich zweifel nicht an das es so in Echtzeit laufen kann, aber als In-Game geht es SO nicht.
DotProduct
L05: Lazy
- Seit
- 24 Mai 2005
- Beiträge
- 286
Das ist von IBM... Follow the Link oder hat MS jetzt IBM.com auch unter ihrer Kontrolle!
IBM->
http://www-128.ibm.com/developerworks/linux/library/pa-cell/index.html?
Die Aussagen sind von IBM Angstellten, die an einem Linux Port für Cell arbeiten auf der IBM Website.
Viel mehr IBM wird es nicht mehr!
IBM->
http://www-128.ibm.com/developerworks/linux/library/pa-cell/index.html?
Die Aussagen sind von IBM Angstellten, die an einem Linux Port für Cell arbeiten auf der IBM Website.
Viel mehr IBM wird es nicht mehr!
Hier mal der Beweis das Ben O'Sullivan auch was mit Bizarre Creations zu tun hat:
http://www.gamefaqs.com/console/xbox/data/472137.html
Car Art Ben O'Sullivan
September 25, 2003 - As we get closer to Project Gotham Racing 2's release, we'll be showing off as many vehicles as we can, but they're all going to be broken down by class. This way it'll all mean something to the serious racing fans out there. We're merely the conduit for all of this knowledge. Ben O'Sullivan is the Lead Car Artist on the game, and so he's the man when it comes to this stuff.
http://xbox.ign.com/articles/451/451662p1.html
http://www.gamefaqs.com/console/xbox/data/472137.html
Car Art Ben O'Sullivan
September 25, 2003 - As we get closer to Project Gotham Racing 2's release, we'll be showing off as many vehicles as we can, but they're all going to be broken down by class. This way it'll all mean something to the serious racing fans out there. We're merely the conduit for all of this knowledge. Ben O'Sullivan is the Lead Car Artist on the game, and so he's the man when it comes to this stuff.
http://xbox.ign.com/articles/451/451662p1.html
Cell schrieb:
Nein, gutes Fachwissen sollte ausreichen. Komischerweise sind diese Leute genau meiner Meinung. Und nicht zu unrecht frägt sich selbst IBM wieso Sony den Cell einbaut... Aber die Unterschiede wurden hier 1000 mal erklärt warum der Cell hier Kacka ist, aber Du willst es nicht verstehen, deswegen erspare ich mir mehr zu dem Thema.
@Justy
Aha, du weisst also wie der Cell in verbindung mit RSX laufen wird?
Hast du irgendwelche informationen darüber?
Weist du was für eine rolle die SPEs spielen werden?
Ich meine Sony hatt die ja nicht umsonst eingebaut, damit die däumchen drehen
Aha, du weisst also wie der Cell in verbindung mit RSX laufen wird?
Hast du irgendwelche informationen darüber?
Weist du was für eine rolle die SPEs spielen werden?
Ich meine Sony hatt die ja nicht umsonst eingebaut, damit die däumchen drehen
Cell schrieb:@Justy
Aha, du weisst also wie der Cell in verbindung mit RSX laufen wird?
Hast du irgendwelche informationen darüber?
Weist du was für eine rolle die SPEs spielen werden?
Ich meine Sony hatt die ja nicht umsonst eingebaut, damit die däumchen drehen
Anscheinend weiß ich und die IBM Mitarbeiter mehr als Du, und das reicht wohl, oder?
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