1. A computer graphics apparatus, comprising: a) a central processing unit (CPU), wherein the CPU is configured to produce graphics input in a format having an architecture-neutral display list for a sequence of frames; b) a memory coupled to the central processing unit; c) first and second graphics processing units (GPU) coupled to the central processing unit, wherein the first GPU is architecturally dissimilar from the second GPU; and d) a just-in-time compiler coupled to the CPU and the first and second GPU configured to translate instructions in the architecture neutral display list into an architecture specific format for an active GPU of the first and second GPU, wherein the just-in-time compiler is configured to perform a context switch between the active GPU and the inactive GPU, wherein the active GPU becomes inactive and the inactive GPU becomes active to process a next frame of the sequence of frames, and turn off the one of the first and second GPU that is inactive after the context switch.
2. The apparatus of claim 1 wherein the just-in-time compiler is configured to perform the context switch by reading a GPU state from the one of the first and second GPU that is active before the context switch, translating the state to a format of the other GPU of the first and second GPU, and then uploading the state to the other GPU.
3. The apparatus of claim 2 wherein the just-in-time compiler is configured to transfer contents of a video RAM of the GPU that is inactive after the context switch to a video RAM of the GPU that is to be active after the context switch.
4. The apparatus of claim 2 wherein the just-in-time compiler is configured to translate a register state for the GPU that is active before the context switch to a register state format for the GPU that is to be active after the context switch.
5. The apparatus of claim 2 wherein the first GPU is a high power GPU and the second GPU is a low power GPU having lower power consumption than the high power GPU and a maximum processing capacity that is less than a maximum processing capacity of the high power GPU.
6. The apparatus of claim 5 wherein the just-in-time compiler is configured to perform a context switch from the high power GPU to the low power GPU if the high power GPU is the active GPU and the high power GPU is operating at a processing capacity that is less than or equal to the maximum processing capacity of the low power GPU.
7. The apparatus of claim 5 wherein the just-in-time compiler is configured to perform a context switch from the low power GPU to the high power GPU if the low power GPU is the active GPU, the low power GPU is operating at its maximum processing capacity, and a frame render time for the apparatus is decreasing.
8. The apparatus of claim 1, further comprising a display controller coupled to the first and second GPU.
9. The apparatus of claim 8, further comprising an image display device coupled to the display controller.
10. In a computer graphics apparatus having a central processing unit (CPU) and architecturally dissimilar first and second graphics processing units (GPU) a computer implemented graphics processing method, comprising: a) producing graphics input in a format having an architecture-neutral display list for a sequence of frames with the CPU; b) translating by a just-in-time compiler one or more instructions in the architecture neutral display list into GPU instructions in an architecture specific format for an active GPU of the first and second GPU; c) performing graphics processing with the active GPU using the GPU instructions in the architecture specific format for the active GPU; d) displaying one or more images on a display device using signals derived from the active GPU as a result of execution of the GPU instructions in the architecture specific format for the active GPU; e) monitoring a power consumption of the active GPU, f) determining whether to switch between the active GPU and an inactive GPU of the first and second GPU based on the power consumption of the active GPU, g) performing a context switch between the active GPU and the inactive GPU, wherein the active GPU becomes inactive and the inactive GPU becomes active to process a next frame of the sequence of frames, and h) turning off the one of the first and second GPU that is inactive after the context switch.
11. The method of claim 10, wherein performing the context switch includes reading a GPU state from the one of the first and second GPU that is active before the context switch, translating the state to a format of the other GPU of the first and 4 second GPU, and then uploading the state to the other GPU.
12. The method of claim 11, wherein performing the context switch further comprises transferring contents of a video RAM of the GPU that is inactive after the context switch to a video RAM of the GPU that is to be active after the context switch.
13. The method of claim 11, wherein performing the context switch further comprises translating a register state for the GPU that is active before the context switch to a register state format for the GPU that is to be active after the context switch.
14. The method of claim 10 wherein the first GPU is a high power GPU and the second GPU is a low power GPU having lower power consumption than the high power GPU and a maximum processing capacity that is less than a maximum processing capacity of the high power GPU.
15. The method of claim 14 wherein performing the context switch includes performing a context switch from the high power GPU to the low power GPU if the high power GPU is the active GPU and the high power GPU is operating at a processing capacity that is less than or equal to the maximum processing capacity of the low power GPU.
16. The method of claim 14 wherein performing the context switch includes performing a context switch from the low power GPU to the high power GPU if the low power GPU is the active GPU, the low power GPU is operating at its maximum processing capacity, and a frame render time for the apparatus is decreasing.
17. A non-transitory computer readable storage medium, having embodied therein computer readable instructions for implementing a computer graphics processing method in a computer graphics apparatus having a central processing unit (CPU) and architecturally dissimilar first and second graphics processing units (GPU), the method comprising: a) producing graphics input in a format having an architecture-neutral display list for a sequence of frames with the CPU; b) translating by a just-in-time compiler one or more instructions in the architecture neutral display list into GPU instructions in an architecture specific format for an active GPU of the first and second GPU; c) performing graphics processing with the active GPU using the GPU instructions in the architecture specific format for the active GPU; d) displaying one or more images on a display device using signals derived from the active GPU as a result of execution of the GPU instructions in the architecture specific format for the active GPU; e) monitoring a power consumption of the active GPU, f) determining whether to switch between the active GPU and an inactive GPU of the first and second GPU based on the power consumption of the active GPU, g) performing a context switch between the active GPU and the inactive GPU, wherein the active GPU becomes inactive and the inactive GPU becomes active to process a next frame of the sequence of frames, and h) turning off the one of the first and second GPU that is inactive after the context switch.