Can Sony Dominate with Cell?
SCE has begun pushing the Cell microprocessor as its next strategy. If the firm's aim can be realized, the Sony Group could become a semiconductor major.
Can Sony Computer Entertainment Inc (SCE) of Japan pull off its third major success? The first was in 1994, when the company utilized new compact disk read-only memory (CD-ROM) media to shoe-horn itself into a leading position in the home game system market, succeeding in spite of the fact that the market was almost entirely locked up by leaders Nintendo Co, Ltd of Japan and Sega Enterprises Ltd of Japan. The second success was in 2000, when the home game system market was in the doldrums with old technology, and SCE introduced the latest semiconductor technology to attain an unmovable position in the game industry even while being condemned for its "epic game" approach.
But will there be a third success? In 2005, SCE has begun pushing the Cell next-generation microprocessor as its next strategy. The Cell IC is not designed only for use in game systems, but is intended for application in everything from home servers to TVs, mobile phones and workstations. The firm also plans to aggressively push Cell on the merchant market, nurturing technology born from game systems into a platform for diverse networked equipment. If the firm's dream can be realized it will mean that the Sony Group holds a core part of the network era, which could make it into a semiconductor major. This is part of the reason that Ken Kutaragi, executive deputy president and chief operating officer (COO) of Sony Corp of Japan, always seems to mention Intel Corp of the US as a potential competitor in various developments.
Long-Term Strategy
The presentation at the International Solid-State Circuits Conference (ISSCC) 2005, where the Cell was revealed, was standing-room-only as people packed the several hundred seats for a glimpse.
Is Cell really that great? Of the chip outline presented at the conference, the audience was especially intrigued by the very high floating-point operation speed, hitting 256 GFLOPS at 4GHz.
(256 GFLOPS is over 40 times higher than the Emotion Engine mounted in SCE's PlayStation 2, and over 15 times higher than Intel's Pentium 4.)
The real quality of Cell is not in the operating frequency or number-crunching prowess of the prototype chip, however, but in the internal architecture. Advances in semiconductor manufacturing technology and the sharp rise in the number of internal operators have made this structure essential to continue to meet diversifying applications from digital appliances to computers. In addition, engineers are also working on an environment that will make it possible to network multiple Cells together to act like a single computer. The goal is to leverage the chip's flexibility and expansibility to make it a core component for the electronics industry, and keep it that way over the long term. "We wanted to make an architecture that would be valid for at least a decade," said James Kahle, IBM fellow, Broadband Processor Technology, Microelectronics Div, IBM Corp of the US, emphasizing the future-oriented design of the chip. The prototype chip is merely the first step in realizing this goal, merely a starting point.
The basic concept of Cell was firmed up in the spring of 2001, when the joint development lab was established by SCE, IBM and Toshiba Corp of Japan in Austin, Texas. SCE and Toshiba engineers flew to the US for the initial meeting with IBM on the Cell concept, meeting a host of top IBM engineers, such as people in charge of developing the POWER4 server microprocessor. The scale of the development team was gradually boosted to several hundred people, mostly engineers from IBM. The fact that IBM, the former leader in the mainframe world, contributed so heavily to the development of an IC for home game systems clearly demonstrates how the key driver in electronics technology has shifted from computers to home electronics (Figs 1 and 2).
Product Development
The disclosed specs for the prototype chip were not maxed-out data created for the conference. The development team has confirmed operation at up to 5.2GHz on the first prototype chip obtained in April 2004, but the ISSCC presentations on Cell merely stated "4GHz or higher". More than likely, the companies are expecting to use about 4GHz in actual equipment for reasons of higher IC yield, lower dissipation and simplified board design. The initial chip exhibited no problems with logical operations, and was able to boot the operating system (OS). Dissipation, however, was a major issue. Masakazu Suzuoki, VP, Microprocessor Development Dept, Semiconductor Business Div at SCE, feels that this has been resolved: "We had a difficult time reducing dissipation at the start, but finally found the solution in the second half of 2004."
Cell chips will be used in home game systems by SCE, high-definition TV (HDTV)-capable digital TVs and home servers by Sony, and HDTV-capable digital TVs by Toshiba by 2006. Hardware and software for these products is now being developed simultaneously at multiple sites in the US and Japan. Entry into the development areas is strictly controlled, so very few engineers have actually seen Cell chips in operation. In these secret labs there are development boards the size of pillows, mounting twin Cell chips with little air-cooled heat sinks small enough to sit in the palm of your hand. Development is under way on 3D graphic draw libraries for gaming, HDTV demodulation software, and more.
Leading the Era
The Cell chip is a multicore design, single-chipping the general-purpose central processing unit (CPU) core to run the OS and handle other tasks, and multiple signal processors called synergistic processing elements (SPE). The prototype chip has the IBM Power-architecture general-purpose CPU core and eight SPEs.
The circuit configuration has been simplified as much as possible so that the CPU core and the SPEs can operate together at 4GHz or higher. This is because the complex instruction scheduling that has become so common in high-performance microprocessors lately tends to boost core footprints and dissipation both.
The quantity of SPEs per Cell will vary with the performance the equipment requires and the scale of the circuits to be integrated into the chip, but will always be an even number. The CPU core is not dependent on any specific architecture, and ignoring business-related factors could easily be designed to use ARM for mobile phones and MIPS for desktop equipment, for example. In fact, IBM appears to be developing a separate Cell chip using a totally different CPU core.
The Cell design approach based on the simplified CPU core and signal processors is leading the way for design trends in microprocessors as they move towards multicore design. As Justin Rattner, senior fellow, Corporate Technology Group and senior director, Microprocessor Technology Lab at Intel explained, top people in the industry share the same opinion: "In the future, it will be crucial to design microprocessors by single-chipping multiple simple CPU cores."
Flexible Interfaces
The design approach aiming for application in diverse systems is evident in the system interface linking Cell to peripheral ICs, too. The physical layer is the FlexIO high-speed parallel transfer technology developed by Rambus Inc of the US. The interface is 12 bytes wide, with seven bytes used for output and five for input. Depending on the specific peripheral ICs used, the widths can be freely adjusted in 1-byte units, supporting a maximum of two peripheral ICs (Fig 3).
The per-pin peak data rate for FlexIO is a high 6.4 Gbits/s, which is higher than the 2.5 Gbits/s delivered by existing PCI Express serial transfer, or even 5 Gbits/s second-generation PCI Express technology. As a result, the system interface offers a peak data rate of 76.8 Gbytes/s, roughly ten times faster than the Pentium 4.
The adoption of FlexIO seems to have been due in part to the fact that it can be used with inexpensive clock ICs. This is crucial in keeping costs down in consumer electronics products costing hundreds of dollars. FlexIO incorporates a circuit to dynamically ensure clock signal jitter due to supply voltage fluctuation, making it possible to hit a per-pin rate of 6.4 Gbits/s even using clock ICs with relatively high jitter.
Swallowing ASICs
Behind this major shift in design policy are the facts that it is time for another change in architecture, which generally occurs every five years as semiconductor manufacturing technology advances, and that application-specific ICs (ASIC) for individual products pose increased development load.
In the five years since the development of the Emotion Engine semiconductor geometry has shrunk considerably. It has been possible for microprocessors on chips of given areas to boost processing performance by ten times over this period through architecture revamps. This is sufficient to even make the shift to a whole new platform worthwhile. The difference in performance between the prototype Cell and the first-generation Emotion Engine is 40x, but they are about the same size: 221mm2 for the former, and 226mm2 for the latter. This is on a par with the Pentium 4, manufactured with 180nm technology, at 217mm2.
With number-crunching performance of 256 GFLOPS, it becomes possible to implement almost all of the signal processing demanded by digital consumer electronics in software. Encoding demanded by Moving Picture Coding Experts Group Phase 2 (MPEG-2) for standard-definition TV (SDTV), for example, can be executed for several dozen streams in parallel. This means that all of the various signal processing circuits currently implemented in individual ASICs can be replaced by the Cell. For applications like mobile phones where signal processing performance does not need to be very high, the quantity of SPEs can be reduced in a special Cell, cutting chip footprint and dissipation.
Full Use of Silicon
One advantage of the Cell, which can vary the quantity of SPEs to control number-crunching capability, is that it will prove very handy in the future by providing the increasing performance digital consumer electronics needs.
Take H.264 encoding, for example. The prototype chip can handle encoding of multiple SDTV video streams in parallel, but only one HDTV stream. If HDTV imagery is being recorded to Blu-ray Disc media with H.264, for example, the system would require even higher performance in order to be able to simultaneously play a game or execute other applications. Other demands are also being raised calling for boosted performance in digital consumer electronics, such as an image recognition function to make it possible to search for a particular scene within massive imagery records.
With Cell it is possible to develop a microprocessor satisfying the requirements much faster than an ASIC, just by increasing the quantity of SPEs. A large number of signal processing operations in digital consumer electronics are executed in pixel units, making it fairly easy to execute them through parallel processing and gain maximum effect from an increase in SPE quantity.
The fact that performance can be boosted without changing chip size, just by increasing the number of SPEs, also contributes to maintaining a high capacity usage ratio at the fab. If advances in semiconductor manufacturing technology are only used to shrink chips it will be necessary to produce cheap chips in volume, increasing the time needed to recover the capital investment into the facility (Fig 4).
Hardware, Software
Cell is more than just the IC: it only achieves full performance when it is used in conjunction with the software. It will not be a trivial task to apply all the power offered by the nine processors in the Cell, including the CPU core, to add value to the host equipment. Balancing the load effectively between the cores will require writing code from a solid understanding of Cell architecture, and that means sophisticated software technology. As one engineer involved in Cell development commented, "Engineers who have only been involved in developing software for general-purpose microprocessors are going to have to relearn everything from the ground up. People who have been involved in ASIC development might be better suited to writing code for Cell."
Each company is involved in its own software development project, and it appears, for example, that multiple varieties of Linux running on Cell already exist. While the firms cooperated in the development of the microprocessor, they remain rivals when it comes to Cell-driven products in the marketplace.
While software development methodology will have to be revamped for Cell chips, once the constituent technology required for digital consumer electronics development (OS, libraries and such) is available, it should become considerably simpler to actually develop the product. More and more functions can be used in multiple pieces of equipment, including H.264 and other Codec software and graphical user interfaces (GUI). Sony is already applying this development method in TVs mounting the Emotion Engine. By utilizing software libraries originally developed for the PlayStation 2, it was able to quickly develop the GUI used in the PSX, called the cross-media bar (XMB).
Outside Sales
In parallel with the adoption of Cell chips in their own products, it seems likely that the manufacturers will begin to push sales to other firms involved in consumer electronics and computers. The more products equipped with Cell chips, the easier it will be to achieve a distributed environment via networking, and that was one of the original concepts of the Cell development plan.
The Sony Group plans to provide not only Cell, but also peripheral and graphics ICs equipped with all the needed input/output (I/O) interfaces. The strategy makes one think of an Intel for the digital consumer electronics world. The firm will probably also provide homegrown OS and software. As mentioned above, the development of Cell software will not be trivial, but for the consumer electronics manufacturers, releasing product software to the competition would be the kiss of death because, along with the software, hard-won expertise would also be transferred.
In fact, Cell is provided with a framework to prevent such expertise from escaping. A function is implemented in hardware that can make it impossible for the dedicated SPE memory space to be addressed by the CPU core. This function could be used to prevent third parties from analyzing software libraries or other code in the SPEs.
In addition to sales to the merchant market, it is also possible that the Cell system interface could be disclosed. If third-party developers provide the peripheral ICs for use with Cell, it would rapidly increase the range of possible Cell variations.
To convince as many IC manufacturers as possible to make peripheral ICs for use with Cell, one possible strategy is to release the specs free of charge, as Intel did with its peripheral component interconnect (PCI) bus and accelerated graphics port (AGP) specs. It seems more likely that the information will only be released under a license agreement, however, Sony's Kutaragi suggested.
by Rocky Eda and Tomonori Shindo
Source: http://neasia.nikkeibp.com/neasia/001090
