he traditional raster graphics pipeline used by companies such as Advanced Micro Devices Inc. and Nvidia Corp. needs to go in favour of using ray tracing for a new and better way to render graphics, said Justin Rattner, Intel's chief technology officer, speaking at an annual gathering of Intel researchers. Rattner also disclosed a separate effort to extend the C++ programming language for multi-core processors.
"We believe a new graphics architecture will deliver vastly better visual experiences because it will fundamentally break the barrier between today's raster-based pipelines and the best visual algorithms," said Rattner. "Our long term vision is to move beyond raster graphics which will make today's GPU technology outmoded," he said.
Ray tracing
Intel researchers will present a paper on its upcoming Larrabee chip at the Siggraph conference in August, Rattner said. The paper will provide examples of how to create superior images using ray tracing rather than a conventional raster graphics pipeline, he added.
To date Intel has described Larrabee only in general terms as a processor geared for graphics and technical applications made up from many x86 cores with a simplified, in-order pipeline. Larrabee will sport about 100 new x86 instructions including support for vector processing at a TFlop rate.
Although its x86 cores will be able to handle ray tracing jobs, the chip will also support more traditional graphics rendering models for APIs including OpenGL and Microsoft's DirectX.
Ray tracing is a computational intensive method of drawing images based on following rays of light and their collisions with objects. Rasterisation is a traditional method of breaking a scene into many tiny polygons, then drawing and colouring in each shape to give the scene lighting and texture effects.
Larabee promise
Intel said Larrabee will not ship until at least late 2009. Nevertheless it has generated plenty of interest in the graphics community.
"We haven't seen a new discrete graphics chip player in about a decade," said Dean McCarron, principal of Mercury Research who tracks graphics.
Unofficial reports have said Larabee will use 16 cores running up to four threads each and sport a 1024-bit wide memory bus.
Just as Intel is promising a deeper incursion into computer graphics, AMD and Nvidia are already making inroads into high end technical computing applications.
The two companies already ship graphics chips using more than 100 very simple processing cores. The cores can handle either raster graphics jobs or more general-purpose computing tasks for technical applications ranging from astrophysics calculations to medical imaging.
Both AMD and Nvidia are expected to roll out their next generation parts later this month. They will likely pack even more cores into their chips and expand their efforts in technical computing.
For its part, Nvidia already has a "few dozen" technical apps written for its Cuda environment released a year ago that supports high-end general purpose computing on its chips. "This is a time of generating new code," said Dan Vivoli, a senior vice president of marketing for the technical computing effort at Nvidia.
Beyond C++
Nvidia's Cuda provides extensions to the C language to help programmers show what parts of their code could use multiple cores running in parallel. Intel's Rattner disclosed a similar effort based on C++.
Called Ct for "throughput," the Intel effort provides a range of extensions for the C++ language and a runtime compiler that can ease the process of optimising serial code to run on a multi-core CPU. The extensions help identify the data types and operations on them that a program is using so the compiler can automatically spread the jobs across multiple cores.
"We've linked up with a small group of partners to give us feedback on these extensions from different application domains," said Rattner. "Our next step is to take this to being a commercial product, something which seems highly probable," he added.
The project was co-developed with Intel researchers in China and at its Santa Clara, Calif., headquarters. The code also handles vector processing tasks, using Intel's SSE extended instruction set.
- Rick Merritt
EE Times
